1. Field of the Invention
The present invention relates to a digital modulation apparatus for digitally modulating a signal, more particularly to an orthogonal frequency division multiplex (OFDM) modulation apparatus for modulating an OFDM signal having 0 as the amplitude of a specific frequency component, and relates to an OFDM demodulation apparatus for demodulating this OFDM signal.
2. Description of the Related Art
When transmitting digital signals, there are known the methods of phase modulation (PM) or amplitude modulation (AM) of a single frequency carrier wave signal based on a digital signal.
As a specific example of such modulation methods, there are known phase shift keying (PSK) for changing only the phase of the carrier wave signal and quadrature amplitude modulation (QAM) for changing both the phase and the amplitude of the carrier wave signal.
In the above modulation methods, the single frequency carrier wave signal is modulated so as to have an occupied bandwidth of an extent fitting in the transmission hand.
Recently, as a new modulation method, proposal has been made of the modulation method known as the orthogonal frequency division multiplex (OFDM) modulation method.
In OFDM modulation, a plurality of orthogonal carrier wave signals are generated in the transmission band to divide the transmission band and the carrier wave signals are each subjected to PSK processing or QAM processing by digital signals.
Since OFDM modulation divides the transmission band by a plurality of carrier wave signals, the band per carrier wave signal becomes narrow and the modulation time per carrier wave signal becomes long. When the transmission band is the same, however, the overall transmission time obtained as a result of the modulation of each of the plurality of the carrier wave signals is no different from the modulation methods used widely previously, for example, the PSK and QAM methods.
In OFDM modulation, a plurality of carrier wave signals are transmitted in parallel, so the transmission rate per digital data to be transmitted, that is, symbol, becomes slower. In a transmission path with so-called multiple path interference, it is possible to reduce the relative delay time of the multiple path interference wave with respect to the time length for symbols. As a result, OFDM modulated signals are resistant to the effects of multiple path interference. Application of OFDM modulation to transmission of digital signals by earth waves taking advantage of this point is drawing great interest.
For signal processing in OFDM modulation, it is necessary to perform inverse discrete Fourier transformation (IDFT) at a high speed, while for signal processing in OFDM demodulation, it is necessary to perform discrete Fourier transformation (DFT) at a high speed.
In the past, it was difficult to realize such signal processing inexpensively and at a high speed, but recent advances in electronics technology and semiconductor technology have made possible the provision of semiconductor devices which can perform DFT and IDFT efficiently by hardware-like processing and electronic circuits using the same. Accordingly, it has become possible to perform OFDM modulation, or OFDM demodulation, using such semiconductor devices and electronic circuits.
The characterizing feature of OFDM modulation is that orthogonal carrier wave signals are generated for each predetermined bandwidth obtained by dividing a transmission channel (transmission band), but that the OFDM modulated signals are digital signals of a low data transmission rate which can fit in their respective bandwidths and that the individual carrier wave signals are not modulated by digital signals, but all carrier wave signals are modulated all at once by IDFT processing.
A summary of the OFDM modulation will be given below.
On the transmission side performing the OFDM modulation, waveforms of carrier wave signals corresponding to the values "1" or "0" of the digital data to be transmitted are defined for the plurality of carrier wave signals #1 to #n. By adding up and combining the carrier wave signals #1 to #n showing the values of the digital data to be transmitted, OFDM modulated signals are obtained. That is, if these carrier wave signals #1 to #n are arranged in order on the frequency axis and the amplitude and phase of the carrier wave signals are defined by the digital data to be transmitted, it is possible to define the waveform of the data (symbols) of the OFDM modulated signals in a predetermined time length by the digital data to be transmitted.
At the receiving side which demodulates the OFDM modulated signals, the OFDM modulated signals are received and the waveforms of the carrier wave signals are discriminated to establish correspondence with digital data, whereby it is possible to demodulate the OFDM modulated digital data sent from the transmission side for each carrier wave signal.
In OFDM modulation, it is possible to transmit the digital data by defining the carrier wave signals by two phase states and modulating them by the binary PSK (BPSK) method and also possible to define a large number of phases and amplitudes and transmit the data in multilevels.
Digital data given multiple values for each of a plurality of carrier wave signals is transmitted by defining the amplitude and phase of the carrier wave signals and obtaining the waveforms of the same. The processing operation for obtaining the waveforms is the so-called IDFT processing. Therefore, in OFDM modulation, it is possible to obtain an OFDM modulated signal using an IDFT circuit.
Conversely, the OFDM modulated signals obtained by IDFT processing in this way can be demodulated by DFT processing on the receiving side.
An explanation will be next made of the configuration and operation of the OFDM demodulation apparatus 85 for receiving and demodulating the OFDM modulated signal referring to FIG. 1.
FIG. 1 is a view of the configuration of the OFDM demodulation apparatus 85.
The OFDM demodulation apparatus 85 is comprised of an antenna 851 for receiving a radio frequency (RF) signal 850, a tuner 852, multipliers (frequency converters) 853 and 854, a local oscillator 855, a 90.degree. phase shifter (or hybrid circuit) 856, low pass filters 857 and 858, analog to digital (A/D) converters 861 and 862, serial to parallel (S/P) converters 859 and 860, a DFT circuit 863, parallel to serial (P/S) converters 864 and 865, buffer memories 866 and 867, a carrier wave signal reproduction circuit 868, and a bit timing recovery (BTR) circuit (or clock reproduction circuit) 869 for generating a reproduction clock signal.
FIG. 2 is a graph showing the format of an OFDM modulated signal.
The RF input signal 850 input to the receiving antenna 851 is an OFDM modulated signal. In the RF input signal 850 is inserted a synchronization symbol as shown in FIG. 2.
The synchronization symbol is inserted at a predetermined position in the format of the OFDM modulated signal, for example, at the header of the format. To distinguish it from other valid symbols, it is a symbol comprised of a "null signal" of no signal meaning. This synchronization symbol is used for frame synchronization in the stage of OFDM demodulation and for reproduction of the clock signals.
The synchronization symbol can be easily inserted by making a fixed value the portion corresponding to the synchronization symbol in the original input signal of the transmission apparatus, for example, in the case of a binary signal, the I-phase (I) channel signal and the quadrature (Q) channel signal.
As a result of demodulation of the RF signal 850 in the OFDM demodulation apparatus 85, the digital I channel signal 871 and Q channel signal 872 are output from the buffer memories 866 and 867. Preferably, the buffer memories 866 and 867 remove the guard intervals from the I channel signal 871 and the Q channel signal 872.
An explanation will next be made of the operation of the OFDM demodulation apparatus 85.
The RF signal input 850 having the synchronization symbol inserted in it is captured by the receiving antenna 851 and applied to the tuner 852.
The tuner 852 converts the received RF input signal 85 in frequency to an intermediate frequency band (IF) signal, amplifies it, and applies it to the multipliers (frequency converters) 853 and 854.
The respective multipliers 853 and 854 receive as input a local oscillation frequency signal of the local oscillator 855 and a 90.degree. phase shifted local oscillation frequency signal obtained by shifting the output signal of the local oscillator 855 90.degree. in phase by the 90.degree. phase shifter 856. These frequency signals and the output signal of the tuner 852 are multiplied, the IF signal output from the tuner 852 is converted in frequency to a base band signal, and the I channel signal and Q channel signal with the 90.degree. phase difference (orthogonal relationship) are separated from it.
These two base band signals with the 90.degree. phase difference, that is, the I channel base band signal and the Q channel base band signal, are cleared of their high frequency components by the low pass filters 857 and 858 and applied to the A/D converters 859 and 860.
The low frequency base band signals output from the low pass filters 857 and 858 are converted to digital signals in the A/D converters 859 and 860 and are further converted to parallel signals by the S/P converters 861 and 862 and then are applied to the DFT circuit 863.
The two signals converted to digital parallel signals are selected in the DFT circuit 863 based on the DFT time window signal applied from the BTR circuit 864 and DFT processing is performed on the selected portions.
The DFT time window signal is, as mentioned later, produced by dividing to 1/M the clock signal reproduced in the BTR circuit 864.
The results of the DFT processing on the two orthogonally related I and Q signals in the DFT circuit 863 are converted related I and Q signals in the P/S converters 864 and 865 output to the buffer memories 866 and 867 and the carrier wave signal reproduction circuit 868.
The carrier wave signal reproduction circuit 868 reproduces the carrier wave signals based on the two input DFT signals and using these reproduced carrier wave signals controls the local oscillator 855 to make local oscillation signals be generated from the local oscillator 855. More specifically, the carrier wave signal reproduction circuit 868 has a Costas loop circuit. The local oscillator 855 generates the carrier wave signals using the signals from the Costas loop circuit.
The BTR circuit 869 generates a clock signal CLK defining the timing of the processing in the DFT circuit 863 etc. based on the low frequency base band signals output from the low pass filters 857 and 858 and generates the DFT time window signal to the DFT circuit 863.
The two orthogonal signals converted to serial signals in the P/S converters 864 and 865 are processed to remove the guard intervals added at the time of the OFDM modulation and are output from the buffer memories 866 and 867 as the digital format I channel signal 871 and Q channel signal 872 with a phase difference of 90.degree. (orthogonal).
To correctly demodulate the OFDM modulated signal received at the receiving side, it is necessary to correctly reproduce the carrier wave signals and clock signal and to correctly generate the DFT time window timing (phase) used in the DFT processing.
To enable correct generation of the DFT time window at the receiving side, the transmission is performed with the insertion of a null signal synchronization symbol at the header of the frame of the OFDM modulated signal. This synchronization symbol is detected at the receiving side, synchronization is performed by the Costas loop circuit or other phase locked loop (PLL) circuit in the carrier wave signal reproduction circuit 868, and the symbol clock is reproduced or use is made of the same as a reference signal for synchronization of the DFT time window.
Below, an explanation will be made of the configuration of the frame of the OFDM modulated signal and the configuration and operation of the BTR circuit 869 referring to FIG. 2 and FIG. 3.
In this example, as shown in FIG. 2, the synchronization symbol is placed before the first symbol in the frame configuration of the OFDM modulated signal.
The BTR circuit 869 shown in FIG. 3 is comprised of a synchronization symbol detection circuit 880 and a PLL circuit 890. The synchronization symbol detection circuit 880 detects the synchronization symbol shown in FIG. 2 from the low frequency base band signals output from the low pass filters 857 and 858 shown in FIG. 1. The PLL circuit 890 generates the clock signal CLK and the DFT time window signal based on the synchronization symbol detection signal detected by the synchronization symbol detection circuit 880.
The synchronization symbol detection circuit 880 is comprised of doublers 881 and 882, amplitude comparators 883 and 884, a reference value output circuit 885, an AND circuit 886, and a pulse cancel circuit 887 having a mono-multi vibrator.
The output signals of the low pass filters 857 and 858 are applied to the doublers 881 and 882 of the synchronization symbol detection circuit 880. The square values of the amplitude voltages of the input signals, that is, the instantaneous energies of the I and Q signals, are calculated at the doublers 881 and 882 and these instantaneous energies are applied to the amplitude comparison circuits 883 and 884.
In the amplitude comparison circuits 883 and 884, these square values are compared with the reference value REF output from the reference value output circuit 885. When a square value is lower than the reference value REF, it is considered that the synchronization symbol is detected and the logical value 1 is output. That is, in the period of existence of the synchronization symbol, the output signals of the low pass filters 857 and 858 become the null signal (0 V), so the logical value 1 is output from both the amplitude comparators 883 and 884.
The logical AND of the output signals of the amplitude comparison circuits 883 and 884 is taken at the AND circuit 886. When the synchronization symbol is detected, the output signal of the AND circuit 886 becomes the logical value 1. The result of the AND operation is applied to the pulse cancel circuit 887.
Even in the period of data from the first symbol to the (N-1)th symbol shown in FIG. 2, there are sometimes cases due to the effects of noise, the effects of multiple path interference, etc. where the output value of the AND circuit 886 becomes the logical value 1 for an instant as if the synchronization symbol were present.
The pulse cancel circuit 887 accurately detects the synchronization symbol by canceling the pulses generated when the output signal of the AND circuit 886 becomes the logical value 1 for an instant at periods other than that of the synchronization symbol and outputs the result to the PLL circuit 890 as the synchronization symbol detection signal. The pulse cancel circuit 887 is comprised of a circuit comprised of a combination of a low pass filter and a waveshaping circuit for example.
The PLL circuit 890 is comprised of a phase comparator 891, a low pass filter 892, a voltage controlled oscillator (VCO) 893, a 1/M frequency divider 894, and a 1/N frequency divider 895.
The VCO 893 generates a clock signal CK, the 1/M frequency divider divides the clock signal CK to 1/M to generate the time window signal, and the 1/N frequency divider 895 generates a timing pulse for detecting the synchronization symbol. Details of this operation are explained below.
The synchronization symbol detection signal output from the synchronization symbol detection circuit 880 is input to the phase comparator 891, where it is compared in phase with the signal output from the 1/N frequency divider 895. The phase error output from the phase comparator 891 is filtered by the low pass filter 892 and applied to the VCO 893. The VCO 893 generates a clock signal CK of a frequency corresponding to the output signal voltage of the low pass filter 892. The clock signal CK is divided in frequency to the 1/M frequency by the 1/M frequency divider 894 and is output as the DFT time window signal to the DFT circuit 863 and further is divided to the 1/N frequency at the 1/N frequency divider 895 and input to the phase comparator 891.
The N defining the 1/N frequency division ratio of the 1/N frequency divide 895 matches with the number N of symbols, including the synchronization symbol, in the frame of the OFDM modulated signal shown in FIG. 2. When the frame configuration is changed, the frequency division ratio of the 1/N frequency divider 895 is changed along with it.
When the above-mentioned OFDM modulated signal is transmitted in the format of a radio wave signal, there is the possibility of multiple path interference or large noise or other external disturbances for example in the transmission path.
In a transmission path suffering from such external disturbances, the components of the symbols adjoining the synchronization symbol leak into the period of the synchronization symbol or noise ends up entering into the synchronization symbol period, so it is sometimes difficult at the receiving side to accurately detect the synchronization symbol included in the RF input signal 850.
Further, since it is not possible to transmit effective data in the period of the synchronization symbol, the request has been made, from the standpoint of the efficiency of the data transmission, that the synchronization symbol be made as small as possible.
Conversely, however, there is the problem that reduction of the period of the synchronization symbol is not desired from the standpoint of the stability of the PLL circuit 890 defining the timing of operation of the OFDM demodulation apparatus on the receiving side since the signal required for synchronization at the PLL circuit 890 becomes shorter.